State machine design, test and verification tools

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visualSTATE® is a suite of graphical tools for state machine design, test and verification of event-driven systems; use it for any 8-, 16- or 32-bit target microcontroller and even Microsoft® Windows® applications. With visualSTATE, each development phase becomes much easier.


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image of Visual State

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Benefits of model-driven design

  • Design an embedded application by drawing objects, events, actions etc, using the powerful notation of hierarchical UML state charts and state machines.

  • Discuss the design and exchange ideas with others thanks to the model-driven design approach and the graphical design representation.

  • Simulate and visualise your application to find mistakes early in the design cycle.

  • Verify the logical consistency of your designs run-time model with the extremely powerful formal verificator.

  • Perform extensive tests continuously and iteratively throughout your development: validation of the state machine behavior, regression testing and automatic test coverage reporting.

  • Use the power of executable UML and RealLink to execute and visualise the behavior of your state machines on the target system.

  • Automatically generate error-free micro-tight C/C++ code that is 100% consistent with your design.

  • Develop incrementally, reusing code and prototyping.

  • Add new functionality to an existing application as market requirements change.
  • Maintain an existing application thanks to the accurate, structured documentation that is always in-sync with the final design.

Last Updated: June 19, 2007 11:07

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