is designed and tested to cleanly handle unexpected system resets. If a
write had been initiated when the system was reset then if it was not
complete the old state of the logical sector being addressed will be
presented on start-up. If the write operation was complete then the new
state of the logical sector will be read. There are no in between
states or complex recovery procedures required.
devices suffer from wear – that is the repeated use of a particular
area of flash increases the likelihood that it will fail. Distributing
the usage of blocks across the whole flash array greatly increases the
lifetime of NAND devices but effective wear levelling is a complex
task. Seemingly “obvious” algorithms tend to fail in real world
testing. HCC have developed sophisticated wear algorithms (both static
and dynamic) which are tuneable to your systems needs. These ensure
that all the blocks in a NAND flash array are written to evenly within
a configurable maximum distance metric.
Supported NAND Devices
has been designed and tested to work with most types of NAND flash
currently available. NAND flash is constantly evolving and HCC work to
ensure that the product works with the latest technology. The system is
tested in-house on Samsung, ST Micro and Micron devices. It has been
successfully ported to several other types including Toshiba and Hynix.
The system has been extensively tested on both 528 byte page and 2112
byte page devices.
To verify if your target device is supported please send mail to email@example.com
also provide a version of EFFS-FTL for use with Atmel DataFlash.
EFFS-FTL-DF can be used to handle arrays of Atmel DataFlash devices
eficiently while giving them excellent wear characteristics.
Additonally ECC (error correction codes) can be used to correct bit
EFFS-FTL-DF only works with Atmel DataFlash
which has the "spare area" - i.e. those with 528 or 1056 byte page
size. An additional feature of this system is that it can enhance
performance of your system - one reason is that the FTL will use block
erase rather than individual page erases which are considerably faster.
is extensively tested both on real NAND flash systems and in
simulation. Because wear analysis and fail safe safety in particular
are both complex, HCC have developed a complete PC simulation
environment to run millions of test cases to verify both the wear and
fail safe characteristics FTL.
Upper Layer Interface
FTL is designed to be easy to use by standard file systems – and
provides a very simple logical sector based interface for the higher
level application to use. The interface functions are:
||Initialises the FTL
||Performs an initial low-level format of the flash
||Returns the number of logical sectors in the system
||Opens one or more sectors for a read/write operation
||Closes an operation
||Reads a number of logical sectors from the flash
||Writes a number of logical sectors to the flash
interface is suitable for use in conjunction with FAT, THIN and/or
EUSB-MS. Integrated projects can be provided on request.
Physical Device Interface
has carefully designed to work with most NAND flash types and creating
the interface to a aprticular device is straightforward. The FTL
requires some functions for accessing the NAND flash device to be
provided – included with the package are sample drivers for several
NAND flash types though the interface is designed to be easy to port to
any NAND device. Also included are sample ECC algorithms – though where
possible these are best done with hardware support. The interface
functions - called by FTL - that the lower level interface must provide
||Initialises physical layer and gets config info
||Erases a flash block
||Writes a flash page from two buffer pointers
||Reads a flash page